Performance Trace Tools
Brought to you by Adapticom, Inc., and Sublogic, Inc.
Last Revised 11/13/02
"REALTIME" Performance Trace Tools based on off the shelf components integrated with custom designed hardware and software.
Best choice for collection of data used in Trace Driven Simulations.
This is THE technique that:
- Eliminates the problem of inadequate logic analyzer depth, which results in traces of insufficient length.
- Eliminates the need to stop the system while waiting for the analyzer to unload data.
- Eliminates the need to stop the clients driving the system under trace.
- Eliminates the need for any software modifications or "hooks", which can distort results.
For those who are interested in collecting traces exceeding 4.53
billion bus transactions or utilizing software "hooks" in the operating
system,
click
HERE.
Adapticom's trace tools are made up of six basic hardware components:
trace tool data probe
Realtime Data Storage Unit
- Validation Unit
- Intermediate Storage Unit
- Long-term Data Storage Unit
- Post Processing/Modeling Unit
Typically, some custom hardware design is involved in components one and two, while components three through
six are available as "off the shelf" items. A variety of custom software programs control the whole system.
Specific trace tools
are created by identifying a point within the target system from which
the client would like
to collect data. Through discussions with the client, a determination
is made regarding what data is of interest to the client and
what quantity of the data is required. This information is utilized in
bandwidth calculations for the selection of
a probe and subsequent downstream hardware. Once the site has been
selected and the probe procured, small quantities
of data can be collected as samples.
Some typical sites of interest could be:
- The CPU bus
- The PCI bus
- Cluster Controller
In the above cases a logic analyzer probe from one of the major vendors would be used when available.
When existing probes are unavalable or unsuitable, a custom probe is designed and fabricated.
Some typical examples of trace content from the cpu bus could be:
Some typical examples of target processors could be:
Once the probe and trace content have been selected, the bandwidth and data quantity calculations are used to select or custom
design the "realtime storage unit". As in the case of probes, off the shelf storage units are used when
possible; however, due to the enormous quantities and bandwidth of the data collected, special storage
unit designs are sometimes required.
Either one of our standard products is used, or custom hardware is fabricated to interface between the probe and the realtime
storage unit. The realtime storage unit is then connected to the intermediate-term storage unit via one of
several possible high speed interfaces.
The Validation unit works in parallel with the Probe and Realtime Storage unit to collect an independent subset of samples
which can be used to validate the data collected.
Depending on the specifics of an implementation, data may be transferred from the Intermediate Storage Unit to the remaining
downstream hardware via ethernet or other LAN type interfaces.
Other Sources for Trace Tool Information
- BYU Trace Collection Center
- BYU Address Traces
- BYU Address Traces Techniques
- Itanium, Intel Rolls Out Prototype 64-Bit Processors (http://www.the-view.com/news/1299/0801.html )
- BYU: performance Evaluation Laboratory, Trace Data - PEL (http://pel.cs.byu.edu/text/traces/ )
- Parallel Architecture Research Laboratory (http://atanasoff.nmsu.edu/ )
- Parallel Computing Tools - Execution Analysis (http://www.ani.univie.ac.at/ani/students/x/PVTools-ExeAn.html )
- Cornell Theory Center: Parallel Processing Performance Tools (http://www.tc.cornell.edu/Edu/Talks/Performance/ParallelPerfTools/ )
- Intel - PerfMon: Performance Monitoring Capabilities & Tools (http://developer.intel.com/drg/mmx/AppNotes/perfmon.htm )
- Duke Univ.: Design of an Address Tracing System (http://www.ee.duke.edu/Research/VHDL_tutorial/webtracer/webtracer.html)
- TETRA: A Multi-platform Instruction Trace Analyzer (http://www.cs.wisc.edu/~austin/tetra.html )
- Designing and Building Parallel Programs, by Ian Foster (http://www.mcs.anl.gov/dbpp/ )
- Data Collection (http://www.mcs.anl.gov/dbpp/text/node108.html )
- Performance Tools (http://www.mcs.anl.gov/dbpp/text/node106.html )
- An Introduction to High Performance Computing (http://www.man.ac.uk/hpctec/courses/HPC/hpc_1.html )
- Performance analysis and its impact on design (PAID) (http://www.almaden.ibm.com/journal/rd/413/toctxt.html )
- Roadmap for Katmai, Cascades, Tanner, Xeon, Pentium II Xeon Slot 2 CPU, Celeron, Mendocino, Merced (Compu-Tech Systems Online )
- PROCESSOR SPECS Intel - Pentium II - 32-bit - Server / Workstation (Xeon / Tanner / Cascade) (ugeek.com )
- CPU Review (http://www.cpureview.com/intel.html
)
- Wayne A. Wong and Jean-Loup Baer, "Modified LRU Policies for Improving Second Level Cache Behavior" (http://www.cs.washington.edu/homes/waynew/papers/hpca6-repl_policy.pdf)
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